Offer DescriptionFacing the challenges of our timeHelp us grow and be more impactful !Our 'Integrated Wireless Systems' Business Unit based in Neuchâtel, Switzerland, is currently looking for CAD Layout R D Engineer.DescriptionMissionAs a CAD Layout R D Engineer, you will be played an important role within SwissChips initiative to boots Swiss chip industry. You provide highly competitive analog CAD layout solution meeting the project requirements to maximize design/methodology reusability among projects and to insure on time quality deliveries. Also, you execute and support the design and layout engineering activities across a range of projects targeting a variety of mainly CMOS process nodes, spanning from 0.18um to 22nm and below.ResponsibilitiesCAD (~30%):EDA Back-End Analog (Cadence Siemens): installation, customization, update, support technology watch.Develop automation to improve designer efficiency. Put in place and test design flow.Provide technical support to the design team.Technology watch ' flows and tools including AI for CAD.Participate in Linux design environment.Participate in PDK validation: Assess, configure, and manage deployment of multiple Process Design Kits.Participate in External IP / Libraries : installation, customization, update support.Maintain CSEM Libraries Analog IP DB: customization, update, supportLayout (~70%):Keep hands on layout experience in IC projects.IC layout task execution including acceptance for integration tape out.Support project managers designers in the layout task definition execution (preparation, resources, effort and schedules).Actively participate in the projects to smooth IC layout outsourcing execution and insure that work quality is met upon company flow and using CSEM methodology.Support Group Leader and participate in the IC layout tape out resource planning.Maintain the IC layout expertise state of the art techniques for very advanced CMOS nodes foundries, including mastering of process features/options.Insure that layout work quality is met upon company IC design/quality flow.RequirementsKnow-howAt least a BS in Electrical Engineering and 3+ years of industrial experience with CAD tools and layout.Experience in linux.Experience in EDA Front-End Analog is a plus.Experience in advanced CMOS processes (such as 22nm) is a plus.Experience in analog/RF IC design is a plusCAD tools including Cadence and Mentor for analog design and layout.Good programming skills in scripting languages (shell/bash/phyton/skill scripting).Experience with SVN and/or other design version control tool is a plus.IC Layout experience.Master layout constraints.LVS/DRC/ERC verification, troubleshooting and debug skills.Proficiency in floor-planning activities with block assembly and block level routing.Top-level IC layout experience and tape out experience.Interpersonal skillsTeam player with good written and verbal communication skills.Curious and driven towards innovationAnalytical, autonomous and hands-onStrong communication and interpersonal skills.Working language is English; French and/or German would be an asset.We offerCSEM mission and valuesOur mission is the development and transfer of innovative technologies to the Swiss industry. Our objective is to make an impact on our customers and on society at large in the fields of precision manufacturing, digital technologies and sustainable energy. Our strength is the excellence of our people, about 550 passionate specialists dedicated to innovation and technology transfer. We believe that strong values support the successful development of our organization as well as the harmonious and balanced development of all our employees.We areA unique place between research and industry at the cutting edge of new technologiesAn innovative, non-profit, and employee-driven companyA dynamic, multidisciplinary, and multicultural environmentA solar team focused on enabling solutions to energy challenges for a sustainable worldWorking@CSEM meansbeing part of a passionate communityincredible flexibility, attractive working conditions, and great opportunities of developmentbenefit from a management style based on trust feedback and that favors a work-life balanceIn your application, please refer to myScience and reference JobID 64115.RequirementsAdditional InformationWebsite for additional job detailsWork Location(s)Number of offers available 1 Company/Institute CSEM Country Switzerland City Neuchâtel GeofieldWhere to apply WebsiteContact City2000 Neuchâtel WebsiteStreetRue Jaquet-Droz 1STATUS: EXPIRED